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16Z061_PWM - PWM Pulse Width Modulation Module
FPGA IP Core
16Z061_PWM is a PWM pulse width modulation IP core generating up to 16 PWM signals.
Main Features
- FPGA IP Core
- Up to 16 PWM signals
- Independent configuration of period and pulse
- Wishbone bus interface
Technical Data
Size
- Logic elements (Altera Cyclone device family): min. 80
- Pin count min: 1
- Pin count max: 15
System-Bus Interface
- Wishbone bus interface compliant with Wishbone Specification B.3
- 32-bit data transfer, 33MHz bus frequency
- Supported Wishbone bus cycles
- Single read/write
Functionality
- Pulse width modulation
- Up to 16 PWM signals
- Independent period and pulse configuration
Software
Linux 13Z061-06
MDIS5 low-level driver sources (MEN) for 16Z061_PWM
Windows 13Z061-70
MDIS4/2004 / MDIS5 Windows driver (MEN) for 16Z061_PWM
VxWorks 13MD05-60
MDIS5 System (and Device Driver) Package (MEN) for VxWorks. This software package includes most standard device drivers available from MEN.
QNX 13M000-15
MDIS4/2004 system (and device driver) package (MEN) for QNX, source code. This software package includes most standard device drivers available from MEN.
OS-9 13Z061-06
MDIS5 low-level driver sources (MEN) for 16Z061_PWM
Documentation
Data Sheets