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16Z052_GIRQ - Global Interrupt Controller

FPGA IP Core

This global interrupt controller is a globally usable interrupt controller for FPGA internal bus structures like Wishbone and Avalon. The interrupt controller combines the interrupt requests from all internal IP modules.

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Main Features

  • FPGA IP Core
  • Combination of interrupt requests from system-internal IP Cores
  • Wishbone bus interface
16Z052_GIRQ Product Image

Technical Data

Size
  • Logic elements (Altera Cyclone device family): 100 typ.
  • Pin count min: 1
  • Pin count max: 64
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 32-bit data transfer, 33MHz bus frequency
  • Supported Wishbone bus cycles
    • Single read/write
  • Avalon bus interface compliant with the Avalon Bus Specification
  • 32-bit data transfer, 33MHz bus frequency
  • Supported Avalon bus cycles
    • Single read/write
Interrupt Functionality
Interrupt requests to
  • PCI-interrupt lines
  • Parallel interrupt lines
  • Serial interrupt lines of an embedded programmable interrupt controller (EPIC)

Ordering Information

Documentation

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